of_watchdog

Windowed watchdog timer

Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1

Watchdog timer with run-time timeout, optional kick window (early kicks are violations), pre-timeout warning level and a sticky bite output with cause code for driving the system reset.

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
bite	out	parallel	1

Standards

No external standard applies.

More in timers

ID	Block	Maturity
of_timer	Programmable timer / counter with prescaler	fpga-routed
of_aclint	RISC-V ACLINT	simulated
of_rtc	Real-time clock and calendar	planned
of_timestamp	Global timestamp generator	planned
of_timer_multi	Multi-channel general-purpose timer	planned