IP PortfolioSoC interconnectsystem management
of_sysctrl
System controller
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Chip identification, revision, configuration straps, scratch and general control registers, with write-lock of selected fields.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| straps | in | parallel | 16 | |
| ctrl_out | out | parallel | 64 |
Standards
No external standard applies.
More in system management
| ID | Block | Maturity |
|---|---|---|
| of_bootrom_ctrl | Boot ROM and boot-mode controller | simulated |
| of_pinmux | Pin multiplexer | simulated |
| of_addr_remap | Address remap unit | planned |