IP PortfolioSoC interconnectnetwork on chip
of_noc_link_cdc
NoC link pipeline and clock crossing
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Credit-preserving link register stages and asynchronous link FIFOs for long NoC wires and clock-domain boundaries, including chiplet edge adapters.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| flit_in | in | valid-qualified bus | 128 | |
| flit_out | out | valid-qualified bus | 128 | |
| rx_clk | in | clock | 1 |
Standards
No external standard applies.
More in network on chip
| ID | Block | Maturity |
|---|---|---|
| of_noc_router | NoC router | simulated |
| of_noc_ni_axi | AXI4 NoC network interface | simulated |
| of_noc_gen | NoC topology generator | planned |