RISC-V IOPMP

Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2

I/O physical memory protection checker that validates bus master accesses against requester-ID based memory domains and entries, with error capture.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
s_axi	in	valid-qualified bus	256	AXI4 slave port (AW/W/AR channels)
m_axi	out	valid-qualified bus	256	AXI4 master port (AW/W/AR channels)

Standards

RISC-V IOPMP

More in access control and iommu

ID	Block	Maturity
of_iommu	RISC-V IOMMU	planned
of_mpu_bus	Bus master memory protection unit	planned