IP PortfolioSensing and RFwireless_baseband

of_wl_fronthaul_framer

Radio fronthaul framer

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Packs and unpacks IQ samples, timestamps and control words over CPRI or eCPRI fronthaul transport.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
iq_ininAXI4-Stream64 
framesoutAXI4-Stream64 

Standards

  • CPRI Specification V7.0
  • eCPRI Specification V2.0

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