IP PortfolioSensing and RFwireless_baseband

of_wl_dpd

Digital predistortion engine

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2

Generalized memory polynomial predistorter with observation receiver capture and coefficient adaptation for PA linearization.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
iq_ininAXI4-Stream32 
obs_ininAXI4-Stream32 
iq_outoutAXI4-Stream32 

Standards

No external standard applies.

More in wireless_baseband

IDBlockMaturity
of_wl_nr_ofdm_mod5G NR OFDM modulatorplanned
of_wl_nr_ofdm_demod5G NR OFDM demodulatorplanned
of_wl_nr_chest5G NR channel estimatorplanned
of_wl_mimo_detectorMIMO detectorplanned
of_wl_nr_beam_mgmt5G NR beam management engineplanned
of_wl_nr_prach5G NR PRACH detectorplanned
of_wl_nr_precoder5G NR layer mapper and precoderplanned
of_wl_lte_phyLTE PHY basebandplanned
of_wl_nbiot_phyNB-IoT and LTE-M PHYplanned
of_wl_wifi6_bbWi-Fi 6 basebandplanned