IP PortfolioSensing and RFwireless_baseband

of_wl_ddc

Digital down converter

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

NCO mixing, CIC and FIR decimation chains with programmable rates that move a band of interest to complex baseband.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
samplesinAXI4-Stream32 
iq_outoutAXI4-Stream32 

Standards

No external standard applies.

More in wireless_baseband

IDBlockMaturity
of_wl_nr_ofdm_mod5G NR OFDM modulatorplanned
of_wl_nr_ofdm_demod5G NR OFDM demodulatorplanned
of_wl_nr_chest5G NR channel estimatorplanned
of_wl_mimo_detectorMIMO detectorplanned
of_wl_nr_beam_mgmt5G NR beam management engineplanned
of_wl_nr_prach5G NR PRACH detectorplanned
of_wl_nr_precoder5G NR layer mapper and precoderplanned
of_wl_lte_phyLTE PHY basebandplanned
of_wl_nbiot_phyNB-IoT and LTE-M PHYplanned
of_wl_wifi6_bbWi-Fi 6 basebandplanned