IP PortfolioSensing and RFsonar_ultrasound
of_sonar_tx_bf
Ultrasound transmit beamformer
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Per-channel transmit delay and waveform generation for focused, plane-wave and diverging-wave imaging.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pattern | out | parallel | 64 |
Standards
No external standard applies.
More in sonar_ultrasound
| ID | Block | Maturity |
|---|---|---|
| of_sonar_bf | Sonar and ultrasound receive beamformer | planned |
| of_sonar_bmode | Ultrasound B-mode processor | planned |
| of_sonar_doppler | Ultrasound Doppler processor | planned |
| of_sonar_active | Active sonar signal processor | planned |