IP PortfolioSensing and RFrf_frontend
of_rf_synth
RF frequency synthesizer
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 1
Fractional-N synthesizer with wideband LC VCO bank, quadrature divider and automatic band calibration for transceiver LOs.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| refclk | in | clock | 1 | |
| lo_i | inout | RF | 1 | |
| lo_q | inout | RF | 1 | |
| lock | out | serial | 1 |
Standards
No external standard applies.
More in rf_frontend
| ID | Block | Maturity |
|---|---|---|
| of_rf_lna | Low-noise amplifier family | planned |
| of_rf_pa | CMOS power amplifier | planned |
| of_rf_mixer | Mixer family | planned |
| of_rf_switch | RF switch (SPDT to SP8T) | planned |
| of_rf_phase_shifter | Digital phase shifter | planned |
| of_rf_attenuator | Digital step attenuator | planned |
| of_rf_vga | RF variable gain amplifier | planned |
| of_rf_power_detector | RF power detector | planned |
| of_rf_balun_match | Integrated balun and matching network library | planned |
| of_rf_lo_dist | LO distribution and quadrature generator | planned |