IP PortfolioSensing and RFew_sigint
of_ew_df
Direction finding processor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Phase interferometry and amplitude comparison direction finding with ambiguity resolution across an antenna array.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| channels | in | AXI4-Stream | 256 | |
| bearing | out | valid-qualified bus | 32 |
Standards
No external standard applies.
More in ew_sigint
| ID | Block | Maturity |
|---|---|---|
| of_ew_wb_channelizer | Wideband EW channelizer | planned |
| of_ew_pdw_gen | Pulse descriptor word generator | planned |
| of_ew_deinterleaver | Pulse deinterleaver | planned |
| of_ew_spectrum_monitor | Real-time spectrum monitor | planned |