IP PortfolioSecuritymemory_protection
of_sec_lowlat_cipher
Low-latency block cipher
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Unrolled single-cycle tweakable block cipher (PRINCE or QARMA family) for memory scrambling and pointer authentication.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| blk_in | in | valid-qualified bus | 64 | |
| blk_out | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in memory_protection
| ID | Block | Maturity |
|---|---|---|
| of_sec_mem_encrypt | Inline memory encryption engine | planned |
| of_sec_mem_integrity | Memory integrity engine | planned |
| of_sec_sram_scramble | SRAM scrambling controller | planned |
| of_sec_iopmp | I/O physical memory protection | planned |
| of_sec_bus_firewall | Peripheral access firewall | planned |
| of_sec_mem_tagging | Memory tagging unit | planned |