of_sec_hmac
HMAC engine
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
HMAC-SHA-256/384/512 engine with key sideload and message streaming.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| msg_in | in | AXI4-Stream | 32 |
Standards
- NIST FIPS 198-1
- RFC 2104
- NIST FIPS 180-4
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in hash
| ID | Block | Maturity |
|---|---|---|
| of_sec_sha256 | SHA-224/256 engine | fpga-routed |
| of_sec_sha512 | SHA-384/512 engine | simulated |
| of_sec_sha3 | SHA-3 and SHAKE engine | simulated |
| of_sec_kmac | Masked KMAC engine | planned |
| of_sec_sm3 | SM3 hash engine | planned |
| of_sec_blake2 | BLAKE2 engine | planned |
| of_sec_blake3 | BLAKE3 engine | planned |
| of_sec_kdf | Key derivation function engine | planned |