IP PortfolioSecurityside_channel
of_sec_dual_rail_lib
Dual-rail precharge logic cells
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Standard cell set implementing dual-rail precharge logic for data-independent power consumption in small cryptographic blocks.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
No external standard applies.
More in side_channel
| ID | Block | Maturity |
|---|---|---|
| of_sec_masking_gadgets | Masked logic gadget library | planned |
| of_sec_noise_gen | Power noise generator | planned |
| of_sec_rand_delay | Random delay and dummy operation inserter | planned |
| of_sec_fault_detect | Crypto fault detection wrappers | planned |
| of_sec_iso_ldo | Crypto supply isolation regulator | planned |