IP PortfolioQuantum controlcontrol_plane
of_q_shot_accumulator
Shot accumulator and histogrammer
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Averages IQ traces, counts bitstring outcomes and builds histograms over repeated shots to reduce host data rate.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| iq_in | in | AXI4-Stream | 64 | |
| state_in | in | valid-qualified bus | 64 |
Standards
No external standard applies.
More in control_plane
| ID | Block | Maturity |
|---|---|---|
| of_q_control_processor | QPU control processor | planned |
| of_q_pulse_queue | Timed pulse instruction queue | simulated |
| of_q_host_if | Control plane host interface | simulated |
| of_q_variational_loop | Near-time variational optimiser | planned |
| of_q_entanglement_link | Inter-QPU entanglement link controller | planned |