IP PortfolioQuantum controlsc_readout
of_q_readout_demod
Frequency-multiplexed readout demodulator
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Per-tone digital downconversion, decimation and weighted integration of resonator readout signals producing IQ points per qubit.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| adc_in | in | AXI4-Stream | 256 | |
| iq_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in sc_readout
| ID | Block | Maturity |
|---|---|---|
| of_q_state_classifier | Qubit state classifier | simulated |
| of_q_paramp_pump | Parametric amplifier pump controller | planned |
| of_q_trace_capture | Raw readout trace capture | planned |