IP PortfolioQuantum controlcryo_cmos
of_q_cryo_controller
Low-power cryogenic controller
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Digital pulse sequencer and NCO bank designed for the cooling budget of a 4 K stage, with clock gating and minimal static power.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pulse_out | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in cryo_cmos
| ID | Block | Maturity |
|---|---|---|
| of_q_cryo_ldo | Cryogenic LDO regulator | planned |
| of_q_cryo_dac | Cryogenic DAC | planned |
| of_q_cryo_adc | Cryogenic ADC | planned |
| of_q_cryo_readout_rx | Cryogenic readout receiver | planned |
| of_q_cryo_serdes | Cryogenic serial link | planned |
| of_q_cryo_bias | Cryogenic bias generator | planned |
| of_q_cryo_mux | Cryogenic analog multiplexer | planned |
| of_q_cryo_temp_sensor | Cryogenic on-die temperature sensor | planned |
| of_q_sfq_interface | SFQ to CMOS interface | planned |
| of_q_cryo_clock | Cryogenic clock generator | planned |