IP PortfolioQuantum controlneutral_atom
of_q_camera_detect
Camera-based qubit state detection
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Low-latency image pipeline that sums photon counts in regions of interest from an sCMOS or EMCCD frame and thresholds them into occupancy or state bits.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 64 | |
| occ_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in neutral_atom
| ID | Block | Maturity |
|---|---|---|
| of_q_tweezer_ctrl | Optical tweezer array controller | planned |
| of_q_slm_ctrl | Spatial light modulator controller | planned |