IP PortfolioQuantum controlsc_control
of_q_awg_sequencer
AWG pulse sequencer
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Multi-channel arbitrary waveform sequencer with waveform memory, parametric playback, loops and real-time conditional branching, feeding RF DACs at sample rate.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| dac_out | out | AXI4-Stream | 256 | |
| trig_in | in | parallel | 8 |
Standards
No external standard applies.
More in sc_control
| ID | Block | Maturity |
|---|---|---|
| of_q_drag_gen | DRAG pulse generator | simulated |
| of_q_iq_modulator | Digital IQ modulator | simulated |
| of_q_nco_bank | Phase-coherent NCO bank | simulated |
| of_q_readout_comb | Multiplexed readout tone generator | simulated |
| of_q_flux_ctrl | Flux bias DAC controller | simulated |
| of_q_flux_predistort | Flux pulse predistortion filter | simulated |
| of_q_fluxonium_drive | Low-frequency qubit drive synthesiser | planned |
| of_q_wave_decomp | Waveform memory decompressor | planned |
| of_q_dd_inserter | Dynamical decoupling inserter | planned |