IP PortfolioProcessorsriscv_secure
of_cpu_rv64_cheri
CHERI RV64 application core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
RV64 application core with CHERI capability registers and tagged memory support for spatial memory safety and compartmentalisation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- CHERI ISA v9
- RISC-V RV64GC
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_secure
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_secure | Security-hardened RV32 core | planned |
| of_cpu_cheriot_mcu | CHERIoT capability microcontroller core | planned |
| of_cpu_world_isolation | Hardware world isolation checker | planned |