IP PortfolioProcessorsriscv_cluster
of_cpu_acp
Accelerator coherency port
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Slave port into the cluster L2 that lets accelerators issue I/O coherent reads and writes, including allocation hints and cache stashing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- AMBA ACE-Lite
- AMBA CHI
More in riscv_cluster
| ID | Block | Maturity |
|---|---|---|
| of_cpu_cluster_coherent | Coherent RV64 multicore cluster | planned |
| of_cpu_cluster_tcdm | Shared-memory RV32 compute cluster | planned |
| of_cpu_manycore_tile | Many-core mesh tile | planned |