IP PortfolioInterface PHYsline_xcvr
of_lin_xcvr
LIN transceiver
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 3
LIN physical layer with slope-controlled 12 V bus driver, wake-up detection and dominant timeout.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| lin_bus | inout | analog | 1 | |
| txd | in | serial | 1 | |
| rxd | out | serial | 1 |
Standards
- ISO 17987-4:2016
More in line_xcvr
| ID | Block | Maturity |
|---|---|---|
| of_can_xcvr | CAN / CAN FD transceiver | planned |
| of_rs485_xcvr | RS-485 transceiver | planned |
| of_mil1553_xcvr | MIL-STD-1553 bus transceiver | planned |
| of_arinc429_xcvr | ARINC 429 line driver and receiver | planned |