IP PortfolioInterface PHYsmemory_phy
of_hbm2e_phy
HBM2E PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
HBM2E PHY for silicon interposer attach with 1024 data bits, 8 channels, per-channel training, lane repair and IEEE 1500 test port.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| dq | inout | parallel | 1024 | |
| ca | out | parallel | 256 | |
| dfi_wr | in | parallel | 2048 | |
| dfi_rd | out | parallel | 2048 | |
| wrst | out | parallel | 8 |
Standards
- JEDEC JESD235
- IEEE 1500-2005
More in memory_phy
| ID | Block | Maturity |
|---|---|---|
| of_ddr4_phy | DDR3/DDR4 PHY | planned |
| of_ddr5_phy | DDR5 PHY | planned |
| of_lpddr4_phy | LPDDR4/LPDDR4X PHY | planned |
| of_lpddr5_phy | LPDDR5/LPDDR5X PHY | planned |
| of_lpddr6_phy | LPDDR6 PHY | planned |
| of_gddr6_phy | GDDR6 PHY | planned |
| of_gddr7_phy | GDDR7 PHY | planned |
| of_hbm3_phy | HBM3/HBM3E PHY | planned |
| of_hbm4_phy | HBM4 PHY | planned |
| of_onfi_phy | ONFI / Toggle NAND PHY | planned |