IP PortfolioInterface controllersdisplay
of_vbyone_tx
V-by-One HS transmitter controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
V-by-One HS link layer for TV and large panels with 8b/10b encoding, scrambling, CDR training lock (HTPDN/LOCKN) and lane mapping.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| video | in | AXI4-Stream | 120 | |
| phy_tx | out | parallel | 80 |
Standards
No external standard applies.
Notes
V-by-One HS is a THine Electronics specification; licence terms must be checked.
More in display
| ID | Block | Maturity |
|---|---|---|
| of_hdmi21_tx | HDMI 2.1 transmitter controller | planned |
| of_hdmi21_rx | HDMI 2.1 receiver controller | planned |
| of_dp14_tx | DisplayPort 1.4 source controller | planned |
| of_dp14_rx | DisplayPort 1.4 sink controller | planned |
| of_dp21_tx | DisplayPort 2.1 source controller | planned |
| of_edp_tx | eDP 1.5 transmitter controller | planned |
| of_dsi2_host | MIPI DSI-2 host controller | planned |
| of_dsi_device | MIPI DSI peripheral receiver | planned |
| of_lvds_disp_tx | LVDS display transmitter (OpenLDI) | planned |
| of_parallel_video_out | Parallel RGB / BT.656 / BT.1120 video output | planned |