IP PortfolioInterface controllersusb
of_usb4_router
USB4 router
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
USB4 router with transport layer, configuration space, lane bonding, time synchronisation and adapters for tunnelled USB 3.x, PCIe and DisplayPort traffic.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| lane_tx | out | parallel | 256 | |
| lane_rx | in | parallel | 256 | |
| pcie_tlp | inout | parallel | 256 | |
| dp_stream | in | AXI4-Stream | 128 |
Standards
- USB4 Version 2.0
More in usb
| ID | Block | Maturity |
|---|---|---|
| of_usb_fs_device | USB 2.0 full-speed device | simulated |
| of_usb2_device | USB 2.0 high-speed device controller | planned |
| of_usb2_host | USB 2.0 host controller (EHCI/OHCI) | planned |
| of_usb2_otg | USB 2.0 OTG dual-role controller | planned |
| of_usb3_device | USB 3.2 device controller | planned |
| of_usb3_xhci | USB 3.2 xHCI host controller | planned |
| of_usb3_drd | USB 3.2 dual-role controller | planned |
| of_typec_pd | USB Type-C and Power Delivery controller | planned |