IP PortfolioInterface controllerspwm
of_pwm_motor
Motor-control PWM
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Multi-channel PWM for motor and power-converter control with complementary outputs, programmable dead time, centre-aligned mode, fault inputs with fast shutdown and ADC trigger generation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pwm_h | out | parallel | 6 | |
| pwm_l | out | parallel | 6 | |
| fault_n | in | parallel | 2 | |
| adc_trig | out | serial | 1 |
Standards
No external standard applies.
Notes
Basic PWM already exists as share/iplib/control/of_pwm.