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of_profinet_irt

PROFINET IRT device switch

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3

Two-port PROFINET device switch with RT and IRT scheduling, cut-through forwarding, PTCP time synchronisation and cycle-synchronous application interrupts.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
mii_txoutparallel12 
mii_rxinparallel12 
txinAXI4-Stream32 
rxoutAXI4-Stream32 

Standards

  • IEC 61158 Type 10
  • IEC 61784-2

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IDBlockMaturity
of_ethercat_subEtherCAT SubDevice controllerplanned