IP PortfolioInterface controllerspcie
of_pcie_switch
PCIe switch
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
PCI Express switch with one upstream and multiple downstream ports, internal virtual PCI-to-PCI bridges, routing by address and ID, ACS and peer-to-peer forwarding.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| up_tlp | inout | parallel | 512 | |
| dn_tlp | inout | parallel | 2048 |
Standards
- PCI Express Base 5.0
More in pcie
| ID | Block | Maturity |
|---|---|---|
| of_pcie_g3_ctrl | PCIe Gen3 controller (EP/RP) | planned |
| of_pcie_g4_ctrl | PCIe Gen4 controller (EP/RP) | planned |
| of_pcie_g5_ctrl | PCIe Gen5 controller (EP/RP) | planned |
| of_pcie_g6_ctrl | PCIe Gen6 controller (EP/RP) | planned |
| of_pcie_g7_ctrl | PCIe Gen7 controller (EP/RP) | planned |
| of_pcie_dma | PCIe multi-channel DMA engine | planned |