IP PortfolioInterface controllersnvme
of_nvme_target
NVMe device controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Device-side NVMe controller front end with admin and I/O queue handling, PRP/SGL processing, namespace management and command dispatch to a flash translation layer.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pcie_tlp | in | AXI4-Stream | 512 | |
| cmd | out | AXI4-Stream | 128 | |
| data | out | AXI4-Stream | 512 |
Standards
- NVM Express Base Specification 2.0
- NVM Express over PCIe Transport Specification 1.0
More in nvme
| ID | Block | Maturity |
|---|---|---|
| of_nvme_host | NVMe host initiator | planned |