IP PortfolioInterface controllersmanagement
of_mdio
MDIO management master
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
MDIO/MDC master for Ethernet PHY management supporting Clause 22 and Clause 45 frames with programmable clock divider.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mdc | out | clock | 1 | |
| mdio | inout | serial | 1 |
Standards
- IEEE 802.3-2022