IP PortfolioInterface controllershbm
of_hbm3_ctrl
HBM3/HBM3E memory controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
HBM3 and HBM3E controller with 16 channels of 2 pseudo-channels, on-die ECC reporting, refresh management, ECS and lane repair sequencing over a DFI 5.1 PHY interface.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| host | in | AXI4-Stream | 2048 | |
| phy | out | parallel | 4096 | |
| phy_rd | in | valid-qualified bus | 2048 |
Standards
- JEDEC JESD238
- DFI 5.1
More in hbm
| ID | Block | Maturity |
|---|---|---|
| of_hbm2e_ctrl | HBM2E memory controller | planned |
| of_hbm4_ctrl | HBM4 memory controller | planned |