IP PortfolioInterface controllersflexray
of_flexray
FlexRay communication controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
FlexRay controller with static and dynamic segments, dual channel A/B, clock synchronisation, message buffers and bus guardian interface.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| txd_a | out | serial | 1 | |
| rxd_a | in | serial | 1 | |
| txd_b | out | serial | 1 | |
| rxd_b | in | serial | 1 | |
| txen_n | out | parallel | 2 |
Standards
- ISO 17458-2:2013
- FlexRay Protocol Specification 3.0.1