IP PortfolioInterface controllersauto_ethernet
of_eth_auto_mac
Automotive Ethernet MAC
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 1
10/100/1000 Ethernet MAC for zonal and domain controllers with RGMII/SGMII to 100BASE-T1 and 1000BASE-T1 PHYs, VLAN priority queues, AVB credit-based shaper and gPTP timestamping.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| rgmii_tx | out | parallel | 6 | |
| rgmii_rx | in | parallel | 6 | |
| tx | in | AXI4-Stream | 32 | |
| rx | out | AXI4-Stream | 32 |
Standards
- IEEE 802.3-2022
- IEEE 802.3bw-2015
- IEEE 802.3bp-2016
- IEEE 802.1AS-2020
- IEEE 802.1Qav
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
More in auto_ethernet
| ID | Block | Maturity |
|---|---|---|
| of_eth_t1s_mac | 10BASE-T1S MAC with PLCA | planned |