IP PortfolioInterface controllerssd_mmc
of_emmc_host
eMMC 5.1 host controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
eMMC host with 8-bit bus, HS200 and HS400 enhanced strobe modes, command queuing engine and ADMA3 DMA.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| clk_mmc | out | clock | 1 | |
| cmd | inout | serial | 1 | |
| dat | inout | parallel | 8 | |
| ds | in | serial | 1 |
Standards
- JEDEC JESD84-B51
More in sd_mmc
| ID | Block | Maturity |
|---|---|---|
| of_sd_host | SD/SDIO host controller | simulated |
| of_sdio_device | SDIO device controller | planned |