IP PortfolioPhysical IPspecial-purpose cells
of_sc_power_switch
Header and footer power switch cells
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Daisy-chainable header (PMOS) and footer (NMOS) power gating cells with mother/daughter switches for controlled in-rush current.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| sleep_in | in | parallel | 1 | |
| sleep_out | out | parallel | 1 |
Standards
- IEEE 1801
- Liberty
More in special-purpose cells
| ID | Block | Maturity |
|---|---|---|
| of_sc_retention | State-retention flip-flops | planned |
| of_sc_level_shift | Level shifter cells | planned |
| of_sc_isolation | Isolation cells | planned |
| of_sc_aon | Always-on buffers and inverters | planned |
| of_sc_icg | Integrated clock gating cells | planned |
| of_sc_clock | Clock tree cells | planned |
| of_sc_sync | Synchronizer flip-flop cells | planned |
| of_sc_mbff | Multi-bit flip-flops | planned |
| of_sc_async | Asynchronous logic cells | planned |
| of_sc_dual_rail | Dual-rail precharge logic cells | planned |