IP PortfolioPhysical IPstandard cell libraries
of_sc_hs
High-speed standard cell library
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Taller-track library with larger drive strengths and lower input capacitance for timing-critical paths, footprint-compatible within the family.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- Liberty
- LEF/DEF 5.8
Basis projects
Permissive open projects the implementation may build on.
- SkyWater SKY130 PDK (Apache-2.0)
More in standard cell libraries
| ID | Block | Maturity |
|---|---|---|
| of_sc_hd | High-density standard cell library | planned |
| of_sc_ll | Low-leakage standard cell library | planned |
| of_sc_mvt | Multi-Vt cell variants | planned |
| of_sc_ulv | Near-threshold standard cell library | planned |
| of_sc_radhard | Radiation-hardened cell library | planned |
| of_sc_cryo | Cryogenic standard cell library | planned |
| of_sc_hightemp | High-temperature characterized library | planned |