IP PortfolioPhysical IPnon-volatile memory
of_nvm_antifuse
Antifuse OTP macro
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Gate-oxide breakdown one-time-programmable memory with charge pump, differential bitcells and controller for keys, trim and configuration.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| vpp | inout | analog | 1 |
Standards
No external standard applies.
More in non-volatile memory
| ID | Block | Maturity |
|---|---|---|
| of_nvm_efuse | eFuse macro and controller | planned |
| of_nvm_mtp | Logic-process MTP NVM | planned |
| of_nvm_flash_if | Embedded flash controller | planned |
| of_nvm_rram | RRAM macro | planned |
| of_nvm_mram | Embedded MRAM macro | planned |