IP PortfolioPhysical IPi/o pads
of_io_gpio
General-purpose I/O cell
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 1
Bidirectional LVCMOS pad for 1.8 V, 2.5 V and 3.3 V with programmable drive, slew, pull-up/down, Schmitt input and input enable.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| pad | inout | analog | 1 | |
| a | in | parallel | 1 | |
| oe | in | parallel | 1 | |
| y | out | parallel | 1 |
Standards
- JEDEC JESD8-7A
- JEDEC JESD8C.01
Basis projects
Permissive open projects the implementation may build on.
- SkyWater SKY130 PDK (Apache-2.0)
- GlobalFoundries GF180MCU PDK (Apache-2.0)
More in i/o pads
| ID | Block | Maturity |
|---|---|---|
| of_io_failsafe | Fail-safe and 5 V tolerant I/O | planned |
| of_io_od | Open-drain I2C / I3C I/O | planned |
| of_io_lvds | LVDS I/O cells | planned |
| of_io_cml | CML / LVPECL clock I/O | planned |
| of_io_sstl | SSTL / POD memory I/O cells | planned |
| of_io_analog | Analog pad | planned |
| of_io_rf | RF pad | planned |
| of_io_xtal | Crystal oscillator I/O cell | planned |
| of_io_power | Power and ground pads | planned |
| of_io_corner_filler | I/O corner and filler cells | planned |