of_iiiv_model_pack
III-V compact model pack
Maturity plannedTargets III-V processDifficulty HardPriority 1
Compact models for GaAs/InP pHEMT (Angelov, EEHEMT) and HBT (HiCUM, Agilent HBT) devices delivered as Verilog-A for ngspice and Qucs-S, with extraction reports and corner sets.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- Verilog-AMS 2.4
Notes
Model views only; the skeleton RTL is a placeholder for the IP record.
More in iii_v
| ID | Block | Maturity |
|---|---|---|
| of_inp_mmi_lib | InP MMI and passive photonic component library | planned |
| of_inp_ssc_edge | InP spot-size converter and edge coupler | planned |
| of_iiiv_cal_kit | III-V on-wafer calibration and de-embedding kit | planned |
| of_iiiv_chiplet_bond | III-V on Si flip-chip pad and bump library | planned |
| of_iiiv_thermal_tuner | III-V photonic thermal tuner cell | planned |