IP PortfolioPhysical IPiii-v circuit cell libraries
of_gaas_dcfl_lib
GaAs E/D-mode logic cell library
Maturity plannedTargets III-V processDifficulty Very hardPriority 2
Direct-coupled FET logic cells (inverter, NOR, latch, flip-flop, buffers) built from enhancement and depletion pHEMTs for on-MMIC control logic.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- Liberty
Notes
Dyber, Inc. in-house GaAs and InP process; device models and rules come from the dyber_iiiv PDK and run-1 measurements.
More in iii-v circuit cell libraries
| ID | Block | Maturity |
|---|---|---|
| of_inp_cml_lib | InP HBT CML/ECL logic cell library | planned |
| of_iiiv_esd | III-V ESD protection cells | planned |