IP PortfolioDatapath and DSPmatrix and linear algebra
of_transpose
Matrix transpose and corner-turn buffer
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Block transpose of streamed matrices using multi-bank RAM with conflict-free addressing; used for 2D FFT and radar range-Doppler corner turns.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | AXI4-Stream | 64 | |
| m_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in matrix and linear algebra
| ID | Block | Maturity |
|---|---|---|
| of_systolic_mm | Systolic matrix multiply array | planned |
| of_qr_givens | QR decomposition (Givens rotations) | planned |
| of_cholesky | Cholesky decomposition and solver | planned |
| of_mat_inv | Matrix inversion unit | planned |