IP PortfolioDatapath and DSPrandom number generation
of_prbs
PRBS generator and checker
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Parallel PRBS7, 9, 11, 15, 20, 23 and 31 pattern generator and checker with error counter and lock detection for link test.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| m_out | out | parallel | 64 | |
| chk | in | parallel | 64 |
Standards
- ITU-T O.150
More in random number generation
| ID | Block | Maturity |
|---|---|---|
| of_lfsr | LFSR (Fibonacci / Galois) | simulated |
| of_xoshiro | xoshiro / xoroshiro PRNG | planned |
| of_awgn | Gaussian noise generator | planned |