IP PortfolioDatapath and DSPfloating point
of_fp_transc
Floating-point transcendental unit
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
binary32 exp, log, sin, cos, reciprocal and reciprocal square root using range reduction and polynomial approximation with documented ulp error bounds.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| x | in | valid-qualified bus | 32 | |
| y | out | valid-qualified bus | 32 |
Standards
- IEEE 754-2019
More in floating point
| ID | Block | Maturity |
|---|---|---|
| of_fp_add | Floating-point adder/subtractor | simulated |
| of_fp_mul | Floating-point multiplier | simulated |
| of_fp_round | Floating-point round & pack unit | simulated |
| of_fp2int | Floating-point to fixed-point converter | simulated |
| of_int2fp | Fixed-point to floating-point converter | simulated |
| of_fp_fma | Floating-point fused multiply-add | simulated |
| of_fp_divsqrt | Floating-point divide and square root | simulated |
| of_fp_cmp | Floating-point compare, min/max and classify | simulated |
| of_fp_cvt | Floating-point format converter | simulated |
| of_bf16_dotp | bfloat16 dot-product unit | simulated |