IP PortfolioAnalog and mixed-signaldata_converters
of_ams_adc_sar_hr
High-resolution SAR ADC with calibration
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
16 to 18 bit SAR ADC with capacitor mismatch calibration and optional noise shaping, for precision measurement.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| vin | inout | analog | 1 | |
| vrefp | inout | analog | 1 | |
| samples | out | valid-qualified bus | 18 |
Standards
No external standard applies.
More in data_converters
| ID | Block | Maturity |
|---|---|---|
| of_ams_adc_sar | SAR ADC | planned |
| of_ams_adc_pipeline | Pipelined ADC | planned |
| of_ams_adc_sd_audio | Audio delta-sigma ADC | planned |
| of_ams_adc_sd_precision | Precision delta-sigma ADC | planned |
| of_ams_adc_ti_rf | Time-interleaved RF-sampling ADC | planned |
| of_ams_adc_flash | Flash ADC | planned |
| of_ams_adc_incremental | Incremental ADC | planned |
| of_ams_adc_vco | VCO-based ADC | planned |
| of_ams_adc_housekeeping | Housekeeping ADC with input mux | planned |
| of_ams_dac_cs | Current-steering DAC | planned |