of_acc_tensor_dma

Tensor DMA engine

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

N-dimensional strided DMA with on-the-fly transpose, im2col, padding and broadcast for moving tensors between DRAM and accelerator SRAM.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request

Standards

AMBA AXI4

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