IP PortfolioCompute acceleratorsphotonic
of_acc_photonic_ctrl
Photonic compute mesh controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Digital controller for programmable photonic meshes: phase shifter DAC sequencing, calibration loops and synchronisation of optical input and detection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| dac_codes | out | valid-qualified bus | 256 | |
| pd_codes | in | valid-qualified bus | 256 |
Standards
No external standard applies.
More in photonic
| ID | Block | Maturity |
|---|---|---|
| of_acc_photonic_afe | Photonic compute analog front end | planned |