IP PortfolioCompute acceleratorsnpu
of_acc_npu_tile
Datacenter NPU tile
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Replicable tile combining a matrix engine, vector unit, scratchpad SRAM, tensor DMA and a NoC port for multi-tile training and inference accelerators.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| noc_in | in | AXI4-Stream | 512 | |
| noc_out | out | AXI4-Stream | 512 |
Standards
- IEEE 754-2019
- OCP 8-bit Floating Point Specification (OFP8)
More in npu
| ID | Block | Maturity |
|---|---|---|
| of_acc_systolic_gemm | Systolic GEMM array | planned |
| of_acc_tpu_mxu | TPU-style matrix unit | planned |
| of_acc_conv_engine | Convolution engine | planned |
| of_acc_depthwise_conv | Depthwise and pointwise convolution unit | planned |
| of_acc_winograd_conv | Winograd convolution engine | planned |
| of_acc_attention | Transformer attention engine | planned |
| of_acc_kv_cache_mgr | KV cache manager | planned |
| of_acc_softmax | Softmax unit | simulated |
| of_acc_norm_unit | LayerNorm and RMSNorm unit | simulated |
| of_acc_activation | Activation function unit | simulated |