IP PortfolioCompute acceleratorsnpu
of_acc_nn_preproc
Neural network input preprocessor
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Crop, resize, colour conversion, mean and scale normalisation and layout change of camera frames into tensor format for inference.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 64 | |
| tensor_out | out | AXI4-Stream | 128 |
Standards
No external standard applies.
More in npu
| ID | Block | Maturity |
|---|---|---|
| of_acc_systolic_gemm | Systolic GEMM array | planned |
| of_acc_tpu_mxu | TPU-style matrix unit | planned |
| of_acc_conv_engine | Convolution engine | planned |
| of_acc_depthwise_conv | Depthwise and pointwise convolution unit | planned |
| of_acc_winograd_conv | Winograd convolution engine | planned |
| of_acc_attention | Transformer attention engine | planned |
| of_acc_kv_cache_mgr | KV cache manager | planned |
| of_acc_softmax | Softmax unit | simulated |
| of_acc_norm_unit | LayerNorm and RMSNorm unit | simulated |
| of_acc_activation | Activation function unit | simulated |