IP PortfolioCompute acceleratorsgpu
of_acc_gpu_rasterizer
Rasteriser
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Edge-function triangle rasteriser with hierarchical tiles, coverage masks, MSAA sample patterns and early depth test.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| prim_in | in | AXI4-Stream | 256 | |
| quad_out | out | AXI4-Stream | 256 |
Standards
- Khronos Vulkan 1.3
More in gpu
| ID | Block | Maturity |
|---|---|---|
| of_acc_gpu_simt_core | SIMT shader core | planned |
| of_acc_gpu_tensor_core | GPU tensor core | planned |
| of_acc_gpu_cmd_proc | GPU command processor | planned |
| of_acc_gpu_geometry | Geometry front end | planned |
| of_acc_gpu_texture | Texture unit | planned |
| of_acc_gpu_rop | Render output unit | planned |
| of_acc_gpu_tbdr | Tile-based rendering binner | planned |
| of_acc_gpu_compute | Compute-only GPU cluster | planned |
| of_acc_gpu_raytrace | Ray tracing BVH unit | planned |
| of_acc_gpu_2d | 2D graphics and blitter engine | planned |