IP PortfolioCompute acceleratorsin_memory
of_acc_cim_sram_digital
Digital SRAM compute-in-memory macro
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Custom SRAM macro with bit-serial in-array logic and adder trees performing INT matrix-vector products without moving weights.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in in_memory
| ID | Block | Maturity |
|---|---|---|
| of_acc_cim_sram_analog | Analog SRAM compute-in-memory macro | planned |
| of_acc_cim_nvm | Resistive crossbar compute-in-memory macro | planned |
| of_acc_near_memory | Near-memory processing unit | planned |