IP PortfolioCompute acceleratorsnpu
of_acc_bnn
Binary and ternary network engine
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
XNOR-popcount and ternary MAC engine for binarised and ternary neural networks at very low energy per operation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| act_in | in | AXI4-Stream | 256 | |
| act_out | out | AXI4-Stream | 256 |
Standards
No external standard applies.
More in npu
| ID | Block | Maturity |
|---|---|---|
| of_acc_systolic_gemm | Systolic GEMM array | planned |
| of_acc_tpu_mxu | TPU-style matrix unit | planned |
| of_acc_conv_engine | Convolution engine | planned |
| of_acc_depthwise_conv | Depthwise and pointwise convolution unit | planned |
| of_acc_winograd_conv | Winograd convolution engine | planned |
| of_acc_attention | Transformer attention engine | planned |
| of_acc_kv_cache_mgr | KV cache manager | planned |
| of_acc_softmax | Softmax unit | simulated |
| of_acc_norm_unit | LayerNorm and RMSNorm unit | simulated |
| of_acc_activation | Activation function unit | simulated |